The present application relates generally to an improved data processing apparatus and method and more specifically to an apparatus and method for issuing instructions in-order in an out-of-order processor using false dependencies.
A microprocessor is the heart of a modern computer, a chip made up of millions of transistors and other elements organized into specific functional operating units, including arithmetic units, cache memory and memory management, predictive logic, and data movement. Processors in modern computers have grown tremendously in performance, capabilities, and complexity over the past decade. Any computer program consists of many instructions for operating on data. Processors may be categorized as in-order processors or out-of-order processors.
In-order processors normally process instructions by fetching the instruction, if input operands are available (in registers for instance), dispatching the instruction to the appropriate functional unit or, if one or more operands are unavailable during the current clock cycle (generally because they are being fetched from memory), the processor stalls until they are available, executing the instruction by the appropriate functional unit, and writing the results back to a register file. Out-of-order processors normally process instructions by fetching the instruction, dispatching the instruction to an instruction queue, waiting for operand to be available before issuing the instruction to the appropriate functional unit, executing the instruction by the appropriate functional unit, queuing the results, and only after all older instructions have their results written back to the register file, then this result is written back to the register file. The key concept of out-of-order processing is to allow the processor to avoid a class of stalls that occur when the data needed to perform an operation are unavailable.